(1) Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a high frequency power GaAs Schottky Barrier Field Effect Transistor (hereinafter referred to as "P-GaAs FET") having an internal matching circuit.
(2) Description of the Related Art
A conventional P-GaAs FET of the kind to which the present invention relates is disclosed in, for example, Japanese Patent Application Kokai Publication No. Hei 2-268004, wherein a plurality of GaAs FET chips are combined in a package and an internal matching circuit is provided for matching an input/output impedance to 50.OMEGA.. The internal matching circuit is constituted by a concentrated constant matching circuit and a distributed constant matching circuit, the concentrated constant matching circuit being for impedance matching of individual chips and consisting of a chip capacitor and a bonding wire inductance, and the distributed constant matching circuit being for combining/distributing power in a plurality of chips formed on an alumina substrate. The distributed constant matching circuit is connected, at its connecting portion, with an external input/output lead by bonding wires.
Conventionally, for making alignment with the external lead, the connecting portion of the distributed constant matching circuit is provided with a bonding tab which is a projected tab pattern for the bonding wires to be fixed there.
The conventional semiconductor device described above is shown in a plan view in FIG. 1A, and in a sectional view in FIG. 1B, the sectional view having been taken along line 1B--1B in FIG. 1A. This conventional semiconductor device comprises a package 1 for housing therein the entire structure of semiconductor device, an alumina substrate 2 in which the combining/distributing circuit 3 for input/output power is formed, a chip capacitor 4 for the concentrated constant circuit, a plurality of GaAs FET chips 5, an external lead 6, and a plurality of bonding wires 7 for electrically interconnecting the external lead 6 and the combining/distributing circuit 3.
FIG. 2 is a partially broken and exposed plan view showing the details of the connecting portion at which the substrate 2 and the external lead 6 are connected. The device has a bonding tab 8 which is precisely aligned with a branching point 31 at which the high frequency is balanced and by which the external lead 6 is coupled, by the bonding wires 7, to two transmission paths which are symmetrical between the combining and the distributing portions of the combining/distributing circuit 3 formed on the substrate 2.
As to the dimensions of the bonding tab, the width thereof is normally the same as that of the external lead 6, and the projection from the outer edge disposed at the branching point 31 of the combining/distributing circuit 3 is in the order of 0.3.about.0.5 mm.
During the fabrication of the above conventional semiconductor device, first the external lead 6 and the bonding tab 8 are aligned and are housed in the package 1. Then, the external lead 6 and the bonding tab 8 are interconnected by the bonding wires 7. In this way, the external lead 6 and the combining/distributing circuit 3 are assembled in a precise alignment.
Now, the function of the bonding tab 8 is explained. If the bonding tab 8 does not exist, in the absence of any alignment marker for the branching point 31 in the combining/distributing circuit 3, it is difficult, during the fabrication process, to make alignment in the branching direction (Y direction in FIG. 2) between the external lead 6 and the combining/distributing circuit 3. If the alignment is incomplete or unsatisfactory, the true branching point of the combining/distributing circuit 3 is unbalanced with respect to the inherent high frequency branching point 31, so that the combining and distributing of the transmission power becomes inaccurate resulting in the lowering of gain and output power characteristics. The provision of the bonding tab 8 ensures that the branching point 31 and the actual branching point are easily and accurately aligned in the direction of the branching, and the causes for defective products due to the above described unbalancing are removed.
However, since the bonding tab 8 described above projects from the transmission path of the combining/distributing circuit 3, the transmission path extends by the length of the projection in the direction from the branching point 31 to the external lead 6 (X direction in FIG. 2). Generally, the P-GaAs FET of the kind described above is designed so as to be impedance-matched with a transmission path of 50.OMEGA.. Thus, the branching point impedance at the design frequency of the branching point 31 differs from the 50.OMEGA. impedance of the transmission path to be connected externally when one considers the differences in the inductance of the bonding wire 7 and in the respective dielectric constants of the substrate 2 and the package 1 which the external lead 6 passes through. Therefore, at the connecting point on the bonding tab 8, there arises a phase rotation corresponding to the length of the extension of the transmission path, and this results in a deviation from the design value of the branching point impedance.
In the conventional semiconductor device described above, due to the phase rotation resulting from the transmission path extension corresponding to the length of the bonding tab provided for aligning and connecting the combining/distributing circuit with the external lead, the impedance at the branching point deviates from the design value, and this leads to defective products because of deterioration of output power characteristics and gain characteristics, and to the lowering of yield of products.